Noise Occupancy - S-curves

Prague - Charles University, August 31, 2003

Zdenek Dolezal, Peter Kodys, Zdenka Broklova, Olda Kepka, Pavel Reznicek, Jan Broz

Module: 20220990107653, chips: M0, S1, S2

Measured: 23-31/07/2003

 Default values:

   Module : Link0  Link1  Oddity Chipset DTM SCmode bpm_dr vdac0 vdac1
              1      1      -1      4     1    0     3     700   700
            Select  Vdet  Idet  Vcc  Icc  Vdd  Idd  Vi1  iVi1 Vled0 Iled0 Vled1 Iled1 Vpin Ramp
              0     150.  100.  3.5 1000. 4.0  600.  0.  10.    4.   10.    4.   10.   0.   4

   Chip 0 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   38   100. 15. 30.0   220.0     3
   Chip 1 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   38   100. 15. 30.0   220.0     4
   Chip 2 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   38   100. 15. 30.0   220.0     4
   Chip 3 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   38   100. 15. 30.0   220.0     4
   Chip 4 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   38   100. 15. 30.0   220.0     4
   Chip 5 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   38   100. 15. 30.0   220.0     2
   Chip 6 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   40   100. 15. 30.0   220.0     3
   Chip 7 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   40   100. 15. 30.0   220.0     4
   Chip 8 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   40   100. 15. 30.0   220.0     4
   Chip 9 : Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   40   100. 15. 30.0   220.0     4
   Chip 10: Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   40   100. 15. 30.0   220.0     4
   Chip 11: Comp. Act. Cal_m Trim_r Mask_r Edge Acc. Del. Vth Vcal FEShp. FEBias Role
              1     1     0     0     0    0    0   40   100. 15. 30.0   220.0     2

Results:

zdenka1.gif
NoScurves.ps file
NoPlot.ps file (NO Link 0: 4.33E-6)

Figure like this was observed under default conditions and under each configuration listed below (each number corresponds to different configuration, changes with respect to default are mentioned):

 1. Default (Select = 0  SCmode = 0)
 2. Select = 1  SCmode = 0
 3. Select = 1  SCmode = 2
 4. ACH0 + DCNO + SENSE    BOX+DGND
 5. Chips 3 and 8 were off: FEShp. = 0.0 FEBias = 0.0 Role = 1
 6. Chips 2,4,7 and 9 were off: FEShp. = 0.0 FEBias = 0.0 Role = 1
 7. FEsharper  = 20.0
 8. Vdet = 200.0
 9. Vdd = 3.9
10. Vcc = 3.6
11. Vled0 = Vled1 = 3.0     vdac0 = vdac1 = 750
12. Interconnection between upper and base skeleton of testbox + VME
13. Interconnection between upper and base skeleton of testbox + VME
    + joining with LV card connector
14. Moving with power cable (out of others)
15. Grounding to testbox skeleton
16. Power shielding is grounding independently of others
17. Solid grounding to modulebox
18. Solid grounding to power cable shielding and testbox

s12.gif
NoScurves.ps file
NoPlot.ps file (NO Link 0: 5.19E-6)

Figure like this was observed under each configuration listed below (each number corresponds to different configuration, changes with respect to default are mentioned):

 1. Chips 3 was off: FEShp. = 0.0 FEBias = 0.0 Role = 1
 2. Vcc = 3.4
 3. Opened testbox and 2 modules powered
 4. Signal cables in parallel arangement out of others - opened
    testbox and 2 modules powered
 5. Signal cables in unparallel arangement out of others - opened
    testbox and 2 modules powered

s17.gif
NoScurves.ps file
NoPlot.ps file (NO Link 0: 3.14E-6)

Figure like this was observed under each configuration listed below (each number corresponds to different configuration, changes with respect to default are mentioned):

 1. Signal cables exchanged from recommended ones to Patchcable Cat. 5e,
    UTP, 3P, grey, 3m only for tested module
 2. Signal cables exchanged to Patchcable Cat. 5e, UTP, 3P, grey, 2m
    only for tested module
 3. Signal cables exchanged to Patchcable Cat. 5e, UTP, 3P, grey, 2m
    for both modules
 4. NO scan after longtermtest (10hours): Tchiller = -18oC Thybrid = 7oC,
    standard grounding and signal cables exchanged to Patchcable Cat. 5e,
    UTP, 3P, grey, 2m for both modules

Used grounding and shielding scheme:

AERO board default setting
Patch card: cable screen and modulebox grounded to DGND

Last change: August 31, 2004